1. Field of the Invention
The present invention relates to a semiconductor device and a fabrication method thereof, and more particularly, to a Schottky barrier FinFET (Fin Field Effect Transistor) device and a fabrication method thereof.
2. Description of Related Art
A discrete device such as a MOSFET (Metal Oxide Silicon Field Effect Transistor) having a PN junction structure is being widely used as a switching device of a semiconductor device. Recently, due to demand for high integration and high performance of a semiconductor device, a method of scaling down the MOSFET has been researched. The scaling down of the MOSFET may improve integration density of the semiconductor device, reduce dimensions of the semiconductor device to improve the speed of a switching operation, and reduce distance between devices to improve a signal transmission speed. However, there is a limit to the extent to which the conventional MOSFET may be scaled down. That is, due to the scaling down of the MOSFET, problems result from a gate length, a thickness of a gate insulating layer, an operating voltage, a depth of impurity junctions, and so on. In order to scale down the MOSFET, the gate length should be shorter, the thickness of the gate insulating layer should be thinner, the operating voltage should be lower, and the depth of the impurity junctions should be shallower. However, a short-channel effect may be created when the gate length is shorter, leakage current characteristics should be considered when the thickness of the gate insulating layer is reduced, and a threshold voltage is lowered by lowering the operating voltage. Therefore, since the effects of leakage current of the MOSFET become larger and the impurity junction becomes shallower, resistance characteristics at the junction should be considered. As a result, there is a limit to how far the conventional MOSFET using the PN junction can be scaled down.
Alternatively, instead of the MOSFET using the conventional PN junction, a Schottky barrier tunnel transistor (SBTT) in which a source and a drain are formed using a Schottky junction has been proposed. Since in the SBTT, source and drain regions are formed using a metal, rather than diffusion of impurities, it is possible to form a very shallow junction. In addition, since the SBTT has various advantages such as being capable of reducing parasitic resistance and omitting an ion implantation process due to very low resistance of the metal, the SBTT is being looked to as a next-generation transistor.
An example of the SBTT is disclosed in U.S. Pat. No. 6,744,103 B2, entitled “Short-Channel Schottky Barrier MOSFET Device and Manufacturing Method”, issued to Snyder. According to the Snyder patent, the Schottky barrier MOSFET can be manufactured using a manufacturing method including forming a silicon gate electrode on a semiconductor substrate, forming a thin insulating layer, i.e., oxide sidewalls, covering sidewalls of the silicon gate electrode to a thickness of about 100 Å, and forming source and drain regions on the substrate corresponding to both sides of the silicon gate electrode. In this process, the source and drain electrodes may be formed of a metal silicide layer.
Generally, a process of forming a metal silicide may include depositing a metal layer on a semiconductor substrate, and heat-treating the entire layer to react the metal layer with the semiconductor layer. The metal silicide layer formed as described above may be mainly formed on a surface where the metal layer is in contact with the semiconductor substrate. Therefore, since only a small amount of the metal silicide layer formed on the semiconductor substrate adjacent to the metal layer and not in contact with the metal layer, the oxide sidewalls of the Snyder patent have a small thickness so that the metal silicide layer used as source and drain electrodes can be formed more adjacent to the gate electrode. However, it may be difficult, using this method, to form a thin metal silicide layer, and thus a shallow source and drain junction, while forming the metal silicide layer more adjacent to the gate electrode.